The ShiftRows step operates on the rows of the state; it cyclically shifts the bytes in each row by a certain offset. For AES, the first row is left unchanged. Each byte of the second row is shifted one to the left. Similarly, the third and fourth rows are shifted by offsets of two and three respectively. In this way, each column of the output state of the ShiftRows step is composed of bytes from each column of the input state. The importance of this step is to avoid the columns being encrypted independently, in which case AES would degenerate into four independent block ciphers.Watch the video for practical demonstration using logism.
In the shift rows section, execute circular left shifting for each row.
For first row of box shift 0 step to left, second row of box shift 1 step to left, third row of box shifts two steps to the left and so on.
So after finishing shifting rows, first rows changes from a0.0, a0.1, a0.2, a0.3 to a0.0, a0.1, a0.2, a0.3, second rows changes from a1.0, a1.1, a1.2, a1.3
to a1.1, a1.2, a1.3, a1.0 .Third row changes from a2.0, a2.1, a2.2, a2.3
to a2.2, a2.3, a2.0, a2.1 and so on.
`timescale 1 ns/1 ps module ShiftRows # ( parameter DATA_W = 128 //data width ) ( input clk, //system clock input reset, //asynch active low reset input valid_in, //input valid signal input [DATA_W-1:0] data_in, //input data output reg valid_out, //output valid signal output reg [DATA_W-1:0] data_out //output data ) ; wire [7:0] State [0:15]; //array of wires to form state array genvar i ; generate // filling state array as each row represents one byte ex: state[0] means first byte and so on for(i=0;i<=15;i=i+1) begin :STATE assign State[i]= data_in[(((15-i)*8)+7):((15-i)*8)]; end endgenerate always @(posedge clk or negedge reset) if(!reset)begin valid_out <= 1'b0; data_out <= 'b0; end else begin if(valid_in)begin //shifting state rows as delared in fips197 standard document data_out[(15*8)+7:(12*8)] <= {State[0],State[5],State[10],State[15]}; data_out[(11*8)+7:(8*8)] <= {State[4],State[9],State[14],State[3]}; data_out[(7*8)+7:(4*8)] <= {State[8],State[13],State[2],State[7]}; data_out[(3*8)+7:(0*8)] <= {State[12],State[1],State[6],State[11]}; end valid_out <= valid_in; end endmodule
