2.1 Introduction
The Ethernet IP Core is a MAC (Media Access Controller). It connects to the
Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other.
The core has been designed to offer as much flexibility as possible to all kinds of
applications.
This tutorial describes file hierarchy, description of modules, core design
considerations and constants regarding the Ethernet IP Core.
Knowledge of Logism and verilog HDL is very important to understand the course.
Each chapter consists of three main parts: the logism circuit, the video tutorial and the
verilog code.
2.1 Ethernet IP Core Features
The following lists the main features of the Ethernet IP core.
2.2 Ethernet IP Core Modules
The Ethernet MAC IP Core consists of seven main modules: WISHBONE interface,
transmit module, receive module, control module, MII module, status module and
register module. Many of these modules have sub-modules. Module and submodule operations are described seperately in this tutorial.
