The SOC I would discuss is an advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. The soft core contains a mini UART, two 8-bit timer, read-only memory (ROM) and can also be equipped with the Synchronous Serial Peripheral Interface.

From experience working SOC on FPGA, I can classify their structure into four categories

The Core


The processor above is an 8-bit processor with the control and datapath structure. The SOC can be connected to VGA, RAM, video adapter etc. For this tutorial we will discuss the control and datapath circuitry saperately, and study the cycle which the data_in travels to get to the data_out. The core receives 8 bit data from the SOC top circuitary and generates a 8 bit data output. With a write_enable and read_enable to access the SOC top. The clock and reset signals are used to synchronize the circuitry. The port_addr determines which i/o port to read or write from for a multiport peripheral.

The Data_path

The processor consist of two main sub circuits the the datapath and the control. The datapath is further subdivided into five other subunits:

The datapath cycle:
Input → Data → Regfile → Alu → Shiftbyte → Output.

The cycle above indicates the path of a data signal through the datapath sub circuit to output. The LIFO which stands for last in first out serves as a cache which temporary stores data for the data unit and releases it when needed. The control unit determines the operation carried out on data at every other unit.

Click HERE to download code.

The Control Unit Instruction Set

The sheet below is still being modified