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The ANP

The SOC I would discuss is an advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. The soft core contains a mini UART, two 8-bit timer, read-only memory (ROM) and can also be equipped with the Synchronous Serial Peripheral Interface.

From experience working SOC on FPGA, I can classify their structure into four categories

• 1. The central control bus type: example is the 6805 SOC, which I discussed in a previous tutorial .Find it here. They use an intelligent control bus to relay all information from all parts of the circuitary including ram, i/o ports, cache etc. through a common line to the main processor core.
• 2. The MIPS or fetch-decode-execute type: example is the MIPS, find it here. Data are passed from one stage to another, starting from the fetch to the decode to the execute with some feedback signals which are returned for control.
• 5. The control and datapath type: example is the stack machine, find it here. This is also the type we will talk about today. Here, all the control signals are designed on a different circuitry and the data to be controlled on a different circuit.
• 4. Others

The Core

Features

• 1. 8 Bit ALU
• 2. 8x8 Register File
• 3. 2048x16 Instruction Memory
• 4. 32x8 Ram Memory
• 5. 16x11 Stack Memory
• 6. Three CLK / Instruction
• 7. Carry and Zero flags
• 8. 8 bit Address Port (until 256 Peripherals)

The processor above is an 8-bit processor with the control and datapath structure. The SOC can be connected to VGA, RAM, video adapter etc. For this tutorial we will discuss the control and datapath circuitry saperately, and study the cycle which the data_in travels to get to the data_out. The core receives 8 bit data from the SOC top circuitary and generates a 8 bit data output. With a write_enable and read_enable to access the SOC top. The clock and reset signals are used to synchronize the circuitry. The port_addr determines which i/o port to read or write from for a multiport peripheral.

The Data_path

The processor consist of two main sub circuits the the datapath and the control. The datapath is further subdivided into five other subunits:

• The data
• The Regfile
• The ALU
• The Shiftbyte
• The LIFO

The datapath cycle:
Input → Data → Regfile → Alu → Shiftbyte → Output.

The cycle above indicates the path of a data signal through the datapath sub circuit to output. The LIFO which stands for last in first out serves as a cache which temporary stores data for the data unit and releases it when needed. The control unit determines the operation carried out on data at every other unit.

• 1. The data unit:The data unit consists of seven multiplexers and they are used to make choice of which data to be operated on using signal from the control unit. 8 bit input data from the processor is passed here through the data_in signal. A control signal selk selects this data with the kte data from the control unit. The output signal is fed to a multiplexer which selects it with the shiftout signal from the shiftbyte unit using the insel signal from the control unit, and finally the regmux signal is generated and stored in the Regfile sub unit.

  The carry and zero signal are outputs from the ALU sub unit, and if the ldflag signal from the control unit is turned On, generates the output signals z and c .

  The selpc , ldpc , and ninst_addr signals are all from the control unit and are used to generate the program counter signal also referred to as PC signal. The load program counter signal also called ldpc signal loads the program counter by incrementing the initial value, and if the selpc signal is turned on, then the next instruction address signal also referred to as ninst_addr signal is loaded to the program counter.

  The muximm signal is sent to the B input of the ALU sub unit and is generated by selecting between the portb signal from the Regfile sub unit and the imm data from the control unit using the selimm signal from the control unit.

  The stack_addr signal is generated by incrementing the fifo_out signal from the LIFO sub unit.

• 2. The Regfile: This subunit consists of eight 8-bit data register which is used to store the regmux signal from the data sub unit. If the write enable signal also called we signal which comes from the control unit is turned on, then waa signal will be used to select the particular register to store the data, and this signal is also from the control unit. raa and rab , are read signals from the control unit which are used to determine which register to read into the portA and portB output respectively.
• 3. The ALU: The ALU subunit has eight operations which are controlled or selected using the opalu signal. These operations are performed on A signal which receives its input from portA output of the Regfile subunit and portB which receives its input from muximm output of the data subunit. Each operation generates a zero and carry flag which can be either high or low and fed as input to the data subunit through the zero and carry input respectively. The Result is the output of the ALU operation and is fed to the shiftbyte sub unit through the Din input.
• 4. The Shiftbyte : This sub unit generates the processor data output. It receives the ALU ouput through the Din input and performs different kinds of rotation using the sh signal from the control unit. The rotation can be shift right, shift left, rotate right, rotate left etc. after the rotation the dshift signal is generated. This signal is fed as the processor data output and also fed back to the data sub unit through the shiftout signal.
• 5. The LIFO : This sub unit serves as temporary storage. LIFO stands for LAST-IN-FIRST-OUT. It consists of a RAM that stores data temporary. It operates like a stack; it has two signals which comes from the control unit. The rd_en and wr_en signal, they are used to decrement and increment the ram address respectively. By doing this, PC output from the data sub unit is fed into the DIN input and subsequently stored in the ram when the write enable signal or wr_en is on , and the output dout signal is fed to the fifo_out input of the data sub unit. This signal will later be incremented and used as the stack address fed to the control unit.

Click HERE to download code.

The Control Unit Instruction Set

The sheet below is still being modified