×

Home

Reference

ADC/DAC Conversion techniques

Digital to Analog Converter Overview
the Digital to Analog Converter (DAC) is an interface between the digital signal processing system and the analog world. It is a device that converts digital signals to analog signals (voltage levels, current levels or electric charge).

Connecting digital circuitry to sensor devices is simple if the sensor devices are inherently digital themselves. Switches, relays, and encoders are easily interfaced with gate circuits due to the on/off nature of their signals.

However, when analog devices are involved, interfacing becomes much more complex. What is needed is a way to electronically translate analog signals into digital (binary) quantities, and vice versa. An analog-to-digital converter, or ADC, performs the former task while a digital-to-analog converter, or DAC, performs the latter.

Digital to Analog Data Conversion Tools

• Register: Use to store the digital input.
• Voltage switch: Similar to an ON/OFF switch. It is ‘closed’ when the input is ‘1’. It is ‘opened’ when the input is ‘0’.
• Resistive Summing Network: Summation of the voltages according to different weighting.
• Amplifier: Amplification of the analog signal according to a pre-determined output voltage range.

Types of DAC

• 1. Binary-Weighted-Input Digital-to-Analog Converter
• 2. Summing Amplifier Converter
• 3. The R/2R DAC (Digital-to-Analog Converter)

1. Binary Weighted Resistor
Utilizes a summing op-amp circuit.
Weighted resistors are used to distinguish each bit from the most significant to the least significant
Transistors are used to switch between Vref and ground (bit high or low)

• The classic inverting summer circuit is an operational amplifier using negative feedback for controlled gain, with several voltage inputs and one voltage output.
• The output voltage is the inverted (opposite polarity) sum of all input voltages
• For a simple inverting summer circuit, all resistors must be of equal value.
• If any of the input resistors were different, the input voltages would have different degrees of effect on the output, and the output voltage would not be a true sum.
• Let’s consider, however, intentionally setting the input resistors at different values.
• Suppose we were to set the input resistor values at multiple powers of two: R, 2R, and 4R, instead of all the same value R.

If you recall, the classic inverting summing circuit is an operational amplifier using negative feedback for controlled gain, with several voltage inputs and one voltage output. The output voltage is the inverted (opposite polarity) sum of all input voltages.

For a simple inverting summing circuit, all resistors must be of equal value. If any of the input resistors were different, the input voltages would have different degrees of effect on the output, and the output voltage would not be a true sum.

Voltages V₁ through V_n are either V_ref if corresponding bit is high or ground if corresponding bit is low.
V₁ is most significant bit (MSB) V_n is least significant bit (LSB)

V_out = -IR_f = -R_f ( ^V₁/_R +^V₂/_2R + ^V₃/_4R +.......^V_n/_2^n-1R )

If R_f = R/2

V_out = -IR_f = -R_f ( ^V₁/₂ +^V₂/₄ + ^V₃/₈ +.......^V_n/_2ⁿ )

For example, a 4-Bit converter yields
V_out = -V_ref ( b₃ ¹/₂ + b₂ ¹/₄ + b₁ ¹ /₈ + b₀ ¹ /₁₆)
Where b₃, b₂, b₁, b₀ Corresponds to Bit 3, 2, 1 and 0 respectively.

If we wish to expand the resolution of this DAC (add more bits to the input), all we need to do is add more input resistors, holding to the same power-of-two sequence of values:

Example 1
Calculate the value of V_o, of a 4-bit weighted –resistor DAC, where V_ref = 5V, R = 1kΩ, R_f = 470 Ω, and digital input of 1010 is applied.

Solution:
V_o = -R_f[V_ref ( b₃ ¹/_R + b₂ ¹/_2R + b₁ ¹ /_4R + b₀ ¹ /_8R)]

-R_f[V_ref ( b₃ ⁸/_8R + b₂ ⁴/_8R + b₁ ² /_8R + b₀ ¹ /_8R)]

= ^{470 *5[(8*1) + (4*0) + (2*1) + (1*0)]}/_8*1000 = -2.973V

Binary Weighted Resistor Advantages
Simple Construction/Analysis And Fast Conversion

Disadvantages
1. Requires large range of resistors (2000:1 for 12- bit DAC) with necessary high precision for low resistors
2. Requires low switch resistances in transistors
3. Can be expensive. Therefore, usually limited to 8- bit resolution.

2. Summing Amplifier Converter

• The input resistors have values that are in multiples of 2.
• For example 10k, 20k, 40k, 80k, 160k, 320k etc.
• This gives input gains of one, half, quarter, eighth, sixteenth, etc.
• Binary 0 or 1 values on the input are added together but the gain on each input gives the correct weighting to each bit.
• Binary 0 = 0V
• Binary 1 = 5V

In this diagram if the binary input is 0101, using the summing amplifier formula ...
Vout = -10( 0 / 10 + 5 / 20 + 0 / 40 + 5 / 80 ) = 250 / 80 = -3.125 Volts

Resolution
Resolution is the size of the voltage steps as the digital data is incremented (add one) or decremented (subtract one).
0.625 Volts is the size of the smallest step. This is the resolution of the DAC.

R/2R DAC
R-2R Digital-to-Analogue Converter, or DAC, is a data converter which use two precision resistor to convert a digital binary number into an analogue output signal proportional to the value of the digital number

Starting from the left hand side and using the simplified equation for two parallel resistors and series resistors, we can find the equivalent resistance of the ladder network as:

Resistors R₁ and R₂ are in "parallel" with each other but in "series" with resistor R₃ . Then we can Resolve them in parallel to be in series with resistor R₃ .

R_1&2 = ^{R₁ * R₂} / _{R1 + R2} = ^{2R* 2R}/_{2R + 2R}
=^4R2/_4R = R

Let R_1&2 = R_a
Therefore R_a = R₃ equal to R.
Adding R_a and R₃ in series is equivalent to2R
Now we can see that the equivalent resistance "2R" is in parallel with R₄ with the parallel combination in series with R₅. Resolving 2R in parallel with R₄ = R

Adding it to R₅ in series is equivalent to 2R
The same repeats till R₈.

From voltage divider rule :
V₃ = [^R/_R+R] V₂ = ¹/₂ (V₂).
Likewise,
V₂ = ¹/₂ * V₁
V₁ = ¹/₂ * V_ref
V_out = -IR
Expressing them in terms of V_ref
V₃ = ¹/₈ * V_ref
V₂ = ¹/₄ * V_ref
V₁ = ¹/₂ * V_ref
Therefore, each voltage is half of the preceeding node.
For a 4-bit R-2R Ladder network , we will also have
V₄ = ¹/₁₆ * V_ref
V_out = -R( B₃^V_ref/_2R + B₂^V_ref/_4R + B₁^V_ref/_8R + B₀^V_ref/_16R )
= -V_ref( B₃¹/₂ + B₂¹/₄ + B₁¹/₈ + B₀¹/₁₆ )
For general n-Bit R-2R Ladder or Binary Weighted Resister DAC

Where b₃ corresponds to bit 3, b₂ to bit 2, etc. If bit n is set, b_n =1 If bit n is clear, b_n =0

Advantages
Only two resistor values (R and 2R) and Does not require high precision resistors
Disadvantage
Lower conversion speed than binary weighted DAC

Example 1
For the circuit shown above with Vref = 5V and R = Rf = 2KOhms, calculate the output voltage V0 for an input code word 1110.

V_o = -V_ref * [(8b₃ + 4b₂ + 2b₁ +1b₀) / (16)]
V_o = -5 [(8x1)+(4x1)+(2x1)+(1x0) /16]
= - 5 * (8 + 4 + 2) / 16
= - 4.375 volts

Example 2
Find the output voltage for an R-2R DAC. The digital input is 110. R = 15K, 2R = 30K, R_f= 15K, V_ref= 5V
I_in = ^V_ref/_R = ^5V/_15KOhms = 0.333mA
I₂ = ^V_ref/_2R = ^5V/_{30 KOhms} = 0.1667 mA
I₁ = ^I₂/₂ = ^0.1667mA/₂ = 0.833 mA = 83.33 mA
I_o = I₁ / 2 = 0.0833mA / 2 = 0.04166mA = 41.66mA
I_T = I₂ + I₁ = 0.1667mA + 0.0833mA = 0.25003 mA
V_o = -I_TR_f = -0.25003mA * 15 KOhms = -3.75045 V

Example 3
Output voltage range: This is the difference between the maximum and minimum output voltages expressed in volts.
Calculate the output voltage range of a 4-bit DAC if the output voltage is +4.5V for an input of 0000 and +7.5V for an input of 1111.
Output voltage range = 7.5 - 4.5 = 3.0V

Example 4
Resolution: It is the smallest possible change in the analog output as a result of the change in digital input. Resolution should be as high as possible.
A 4 bit D/A converter have an output range of 0 to 1.5 V. Define its resolution.
Given, n = 4 = number of bits
Full scale output, V_OFS = 1.5V
2ⁿ =2⁴ = 16
Thus the output voltage can have 16 different values including zero.
Resolution: R = ^V_OFS /_2ⁿ-1 = ^1.5/_16-1 = ^1.5/₁₅ = ^100mV/_LSB. Thus, an input change of 1 LSB changes the output by 100 mV.

Sampling a Signal
The carrier signal used to carry data or the clock frequency used to sample data needs to be on a frequency at least double the highest data/music/voice frequency.

The Nyquist Frequency also known as the critical frequency is the highest data/music/voice frequency that can be transmitted. This is half the sampling or carrier frequency.

As the transmission frequency increases, the amount of sampled data that can be encoded also increases. For digital transmissions, UHF and Microwave are preferred over the LF, MF and VHF bands. Fibre-optic is even better due to the exceedingly high frequency of light.

The frequency of light is in the region of 1014 Hz. Theoretically data rates of half this figure should be possible if the light emitting and detecting devices and the fibres could ever be made good enough.

Plenty of Samples - This will work - The original signal can be re-constructed fairly well

Sample and Hold Circuit

Sample and Hold circuits are used to "remember" an analogue voltage for a time period long enough to process the sample. For example if an analogue signal is being converted to digital, the signal must be held for the duration of the conversion.

The simplest circuit could be a single capacitor. This would be satisfactory if there was no capacitor leakage current and the ADC input had a very high input resistance. In addition, there would need to be a way to disconnect the input while the sample was being held.

A better solution is to use a capacitor with a voltage follower. The voltage follower has the required high input resistance and it can drive the ADC input which need not have a high input resistance.

While the switch is open, the capacitor voltage will remain constant assuming there is no leakage current through the capacitor or the op' amp'.

When the switch is closed, the capacitor will rapidly charge to match the input voltage.
For a real life application, the input switch needs to be digitally controlled.
Analogue Switch chips are available. While active, the switch is closed. In the "off" state, the analogue chip has a high output resistance. This effectively disconnects the analogue switch. This ability to disconnect is similar to tristate logic chips which do the same thing.

The CD4066B chip is suitable. It contains four analogue switches. When active, the input is copied to the output. When disabled, the leakage current is about 10 pA (pico-amps).

Analog to digital converters

• Flash ADC
• Digital Ramp ADC
• Successive Approximation ADC
• Tracking ADC
• Slope ADC
• Delta-Sigma ADC

1. Flash Analog to Digital Converter
Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal to a digital signal. Flash ADCs are ideal for applications requiring very large bandwidth, but they consume more power and much bigger in size than other ADC architectures. A Flash converter requires a huge number of comparators compared to other ADCs, especially as the resolution increases. A Flash converter requires 2n-1 comparators for an n-bit conversion.

As the analog input voltage exceeds the reference voltage at each comparator, the comparator outputs will sequentially saturate to a high state. The priority encoder generates a binary number based on the highest-order active input, ignoring all other active inputs. An N-bit flash ADC consists of 2 powered N-1 comparators and contains 2 powered N number of matched resistors and a priority encoder.The circuit below has Vref=4V, The analog input is compared on seven different comparators with different levels (V ₀, V ₁, V₂,V₃, V₄, V₅, V₆). The voltage levels decrease down the line. From KVL:

Assuming all resistors are equal.
V ₀= V _T( R₀/ R _T) = 4*(1/8) = 0.5V
This is also equal to the resolution.
Therefore V ₁, V₂,V₃, V₄, V₅, V₆, V _ref = 1v, 1.5v, 2v, 2.5v, 3v, 3.5, 4v respectively.
V ₁= V _T( R₁/ R _T) = 4*(2/8) = 1V
V ₂= V _T( R₂/ R _T) = 4*(3/8) = 1.5V
V ₃= V _T( R₃/ R _T) = 4*(4/8) = 2V
V ₄= V _T( R₄/ R _T) = 4*(5/8) = 2.5V
V ₅= V _T( R₅/ R _T) = 4*(6/8) = 3V
V ₆= V _T( R₆/ R _T) = 4*(7/8) = 3.5V
V _ref= V _T( R_T/ R _T) = 4*(8/8) = 4V

The priority encoder chart is also given, Starting from I0 to I7. The number of comparators that turns determines the digital output. The number of comparators turn on from i0 to i7 depending on the value of the analog input. The block diagram for the concept is provided below:

Another design of the flash ADC. For this particular application, a regular priority encoder with all its inherent complexity isn't necessary. Due to the nature of the sequential comparator output states (each comparator saturating "high" in sequence from lowest to highest), the same "highest-order-input selection" effect may be realized through a set of Exclusive-OR gates, allowing the use of a simpler, non-priority encoder:

The chart for Comparator output, EX-OR gate output and decoder output is given below.

And, of course, the encoder circuit itself can be made from a matrix of diodes, demonstrating just how simply this converter design may be constructed:

Not only is the flash converter the simplest in terms of operational theory, but it is the most efficient of the ADC technologies in terms of speed, being limited only in comparator and gate propagation delays. Unfortunately, it is the most component-intensive for any given number of output bits.

This three-bit flash ADC requires seven comparators. A four-bit version would require 15 comparators. With each additional output bit, the number of required comparators doubles.

Considering that eight bits is generally considered the minimum necessary for any practical ADC (255 comparators needed!), the flash methodology quickly shows its weakness. An additional advantage of the flash converter, often overlooked, is the ability for it to produce a non-linear output.

With equal-value resistors in the reference voltage divider network, each successive binary count represents the same amount of analog signal increase, providing a proportional response. For special applications, however, the resistor values in the divider network may be made non-equal.

This gives the ADC a custom, nonlinear response to the analog input signal. No other ADC design is able to grant this signal-conditioning behavior with just a few component value changes.

2. Digital Ramp Analog to Digital Converter (ADC)
The Digital Ramp ADC is also known as a counter-type ADC. It uses a binary counter as the register and allows the clock to increment the counter one step at a time until Vo > V+. Circuit shown is a 4 bit Digital Ramp ADC

Circuit Operation

• At the start, the counter is cleared to 0
• As the counter counts up with each clock pulse, the Digital to Analog Converter (DAC) outputs a slightly higher voltage. This voltage is compared to the input voltage by the comparator.
• If the input voltage is greater than the DAC output, the comparator's output will be high and the counter will continue counting normally.
• Eventually, though, the DAC output will exceed the input voltage, causing the comparator's output to go low. This will be the end of conversion and counter output is the adc output.

Notes:

• To observe the operation of the Digital Ramp ADC, first set the Vin
• Press the START button to reset the 4 bit counter and begin the binary counting process
• U5 samples and holds the Vin voltage to V+ of the the comparator (U1) when the START button is pressed. V+ does not change during the conversion process.
• Press the CLK button to observe the results of counter counting up.
• U3 is a 4 bit DAC with step voltage of 0.25V
• EOC LED goes off when the conversion is complete.
• To repeat the process with a different input voltage, press the START button again.

Ramp ADC Problems

• There is a time delay after the start pulse because the counter has to reach the correct value.
• When the comparator changes state, the conversion is complete.
• This could happen quickly or take longer if most of the ramp has to be compared.
• The delay depends on the clock speed and the value of the data input.

Typical ADC Chips
All the components above are built into one chip. This has pins to ...

• SC - start the conversion
• EoC - signal the end of conversion.
  • During the conversion, the output is not valid.
  • The EoC (end of conversion) signal indicates when the conversion is complete.
• OE - enable the output. This is tristate logic. When the output is enabled, the ADC data can be copied to the data bus.

3. Successive Approximation ADC
One method of addressing the digital ramp ADC’s shortcomings is the so-called successive-approximation ADC. The only change in this design is a very special counter circuit known as a successive-approximation register.

Instead of counting up in binary sequence, this register counts by trying all values of bits starting with the most-significant bit and finishing at the least-significant bit. Throughout the count process, the register monitors the comparator’s output to see if the binary count is less than or greater than the analog signal input, adjusting the bit values accordingly.

The way the register counts is identical to the "trial-and-fit" method of decimal-to-binary conversion, whereby different values of bits are tried from MSB to LSB to get a binary number that equals the original decimal number. The advantage to this counting strategy is much faster results: the DAC output converges on the analog signal input in much larger steps than with the 0-to-full count sequence of a regular counter. the circuit looks like this:

The successive-approximation analog-to-digital converter circuit typically consists of four chief subcircuits:

1. A sample-and-hold circuit to acquire the input voltage Vin.
2. An analog voltage comparator that compares Vin to the output of the internal DAC and outputs the result of the comparison to the successive-approximation register (SAR).
3. A successive-approximation register subcircuit designed to supply an approximate digital code of Vin to the internal DAC.
4. An internal reference DAC that, for comparison with Vref, supplies the comparator with an analog voltage equal to the digital code output of the SARin.

Assuming 9v Reference voltage .
Resolution for 4 bit ADC = 9/15 =0.6V
The chart below shows the SAR digital input and the equivalent ADC analog output .